/*
 * File: explicitinvocation_atomicsubsys.c
 *
 * Code generated for Simulink model 'explicitinvocation_atomicsubsys'.
 *
 * Model version                  : 3.0
 * Simulink Coder version         : 9.5 (R2021a) 14-Nov-2020
 * C/C++ source code generated on : Wed Jan  5 11:30:48 2022
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Intel->x86-64 (Windows64)
 * Code generation objectives:
 *    1. Execution efficiency
 *    2. RAM efficiency
 * Validation result: Not run
 */

#include "explicitinvocation_atomicsubsys.h"

/* Block signals and states (default storage) */
DW rtDW;

/* External inputs (root inport signals with default storage) */
ExtU rtU;

/* External outputs (root outports fed by signals with default storage) */
ExtY rtY;

/* Real-time model */
static RT_MODEL rtM_;
RT_MODEL *const rtM = &rtM_;

/* Model step function for TID0 */
void explicitinvocation_atomicsubsys_step0(void) /* Sample time: [1.0s, 0.0s] */
{
  real_T rtb_Sum_nv;

  /* Update the flag to indicate when data transfers from
   *  Sample time: [1.0s, 0.0s] to Sample time: [2.0s, 0.0s]  */
  (rtM->Timing.RateInteraction.TID0_1)++;
  if ((rtM->Timing.RateInteraction.TID0_1) > 1) {
    rtM->Timing.RateInteraction.TID0_1 = 0;
  }

  /* RateTransition generated from: '<Root>/Rate2s' */
  if (rtM->Timing.RateInteraction.TID0_1 == 1) {
    /* RateTransition generated from: '<Root>/Rate2s' */
    rtDW.TmpRTBAtRate2sOutport1 = rtDW.TmpRTBAtRate2sOutport1_Buffer0;
  }

  /* End of RateTransition generated from: '<Root>/Rate2s' */

  /* Outputs for Atomic SubSystem: '<Root>/Rate1s' */
  /* Outputs for Atomic SubSystem: '<S1>/SS2' */
  /* Sum: '<S4>/Sum' incorporates:
   *  Gain: '<S4>/Gain'
   *  Inport: '<Root>/In1_1s'
   */
  rtb_Sum_nv = 2.0 * rtDW.TmpRTBAtRate2sOutport1 + rtU.In1_1s;

  /* End of Outputs for SubSystem: '<S1>/SS2' */

  /* Outputs for Atomic SubSystem: '<S1>/SS1' */
  /* Outport: '<Root>/Out1' incorporates:
   *  Gain: '<S3>/Gain1'
   *  Gain: '<S3>/Gain2'
   *  Inport: '<Root>/In1_1s'
   *  Sum: '<S1>/Sum'
   *  Sum: '<S3>/Sum'
   */
  rtY.Out1 = (3.0 * rtDW.TmpRTBAtRate2sOutport1 + rtU.In1_1s) * 5.0 + rtb_Sum_nv;

  /* End of Outputs for SubSystem: '<S1>/SS1' */
  /* End of Outputs for SubSystem: '<Root>/Rate1s' */

  /* Outport: '<Root>/Out2' */
  rtY.Out2 = rtb_Sum_nv;
}

/* Model step function for TID1 */
void explicitinvocation_atomicsubsys_step1(void) /* Sample time: [2.0s, 0.0s] */
{
  real_T rtb_Integrator;

  /* Outputs for Atomic SubSystem: '<Root>/Rate2s' */
  /* DiscreteIntegrator: '<S2>/Integrator' */
  rtb_Integrator = rtDW.Integrator_DSTATE;

  /* Update for DiscreteIntegrator: '<S2>/Integrator' incorporates:
   *  Inport: '<Root>/In2_2s'
   */
  rtDW.Integrator_DSTATE += 2.0 * rtU.In2_2s;

  /* End of Outputs for SubSystem: '<Root>/Rate2s' */

  /* RateTransition generated from: '<Root>/Rate2s' */
  rtDW.TmpRTBAtRate2sOutport1_Buffer0 = rtb_Integrator;
}

/* Model initialize function */
void explicitinvocation_atomicsubsys_initialize(void)
{
  /* (no initialization code required) */
}

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
